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ADSP-2191 Host Port booting
VHDL design

Version:   1.01
Date:      06.11.2003
Author:    Michael Kuegler
Company:   Analog Devices, Inc.

Target:    Altera MAX7000 EPM7256AETC100-7
Platform:  Altera Quartus II 2.2, SP 2

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This directory contains the VHDL-design described in application note
"ADSP-2191 Host Port booting".
It implements the interface between an ADSP-2191 External Port and an ADSP-2191
Host Port, with a complete separation of both interfaces. The target platform
is an Altera MAX7000 PLD.

Note:   The pin assignment for the project has to be done explicitly, according
        to the assignement in the PCB design.

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Files contained in this directory:

host_2191.vhd      Top level design
hp_sm.vhd          Host Port state machine
ep_sm.vhd          External Port state machine
data_path          Data Path between External Port and Host Port
watchdog.vhd       Watchdog counter
rising_edge        Rising edge detector
pack_const.vhd     Package containing constants


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File hierarchy:

host_2191
  |
  +--- hp_sm
  |      |
  |      +--- pack_const
  |
  +--- ep_sm
  |      |
  |      +--- pack_const
  |
  +--- data_path
  |      |
  |      +--- pack_const
  |
  +--- watchdog
  |      |
  |      +--- pack_const
  |
  +--- rising_edge
         |
         +--- pack_const

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